3D-Test 2013 - Call for Participation

Advance Discount Registration Deadline August 16, 2013!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Workshop Program � The workshop program contains the following elements.

Keynote Address: “3D Solutions in the Coming Age of Terabit Communication” by Nicholas Ilyadis, VP and CTO at Broadcom.
Four sessions with in total 11 paper presentations.
Two panel-discussion sessions
On “Requirements for 3D Volume Production Testing
- On “How Will 3D-Testing Change the Test Supply Chain?”
- A special session with presentations by and discussions with nominees of the
  2013 3DInCites Award in the category Test & Reliability Tools and Equipment.
Continuous display of table-top demos.

Key Dates

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Advance Registration Deadline: August 16th, 2013!

Workshop Registration

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You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes access to all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as far as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments. On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org). Alternatively, register on-site during Test Week at the ITC Registration Counter at the Disneyland Hotel; admission for on-site registrants is subject to availability.

Advance Program

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Thursday -- Friday

September 12, 2013 (Thursday)

4:00 PM - 5:00 PM	Session 1 - OPENING SESSION
4:00 PM	Welcome Address General Chair: Yervant Zorian – Synopsys, USA Program Introduction Program Chair: Erik Jan Marinissen – IMEC, BE
4:15 PM	Keynote: 3D Solutions In the Coming Age of Terabit Communication Nicholas Ilyadis � VP and CTO, Broadcom Infrastructure & Networking, USA As Ethernet switching approaches terabit levels of overall throughput, new paradigms are emerging, along with solutions that encompass 3D fabrication and packaging technologies. TSV/TSI ’s, memory stacks, wafer bonding, heterogeneous device packaging and silicon photonics are driving overall system capacity to new levels. At the same time, these technologies are creating challenges in device testing and yield, downstream final assembly and test, and overall system reliability and serviceability. This talk will target an audience of production and test engineers, exploring technology drivers for 3D solutions and highlighting unique challenges introduced by the progression toward terabit-level communications.

5:00 PM - 5:30 PM	Session 2 - Table-Top Demos
	Demo 1: An Innovative Method for 2.5D/3D IC Interconnection Integrity Monitoring Hans Manhaeve – Ridgetop Europe, BE; Andrew Levy – Ridgetop, USA; Chih-Yang Li – ALLVia, USA Demo 2: Pyramid Probe Card Ken Smith – Cascade Microtech, USA Demo 3: IEEE 1149.1-2013 Support for 3D Stacked Die Brian Turmelle, Mike Ecker, Craig Stephan, CJ Clark – Intellitech, USA Demo 4: Synopsys Synthesis-Based 3D-IC Test Avetik Yessayan, Yervant Zorian, Adam Cron – Synopsys, USA

5:30 PM - 7:00 PM	Session 3 - Panel Discussion: Requirements for 3D Volume Production Testing Moderator: Bill Eklow – Cisco Systems, USA
	Panelists: AMD, Micron, Qualcomm, SanDisk, Samsung, TSMC As the industry prepares for commercialization of 3D ICs, test requirements will vary based on the device being manufactured, and the manufacturer of that device. Panelists from various sectors of semiconductor manufacturing including memory, logic, foundries, and fabless will share their requirements with the test community and answer critical questions.

7:00 PM - 9:00 PM WORKSHOP RECEPTION

September 13, 2013 (Friday)

7:00 AM - 8:00 AM WORKSHOP BREAKFAST

8:00 AM - 8:50 AM	Session 4 - Test Flow and Yield Optimization
8:00 - 8:25	Exploiting Sector-on-Sector Stacking for Yield Improvement of 3D ICs Bei Zhang, Baohu Li, Vishwani Agrawal � Auburn University, USA
8:25 - 8:50	3D Test Flow Modeling and Verification Armin Gr�newald, Michael Wahl, Kai Hahn, Rainer Br�ck � Univ. Siegen, DE

8:50 AM - 10:05 AM	Session 5 - Power to 3D-Test!
8:50 - 9:15	3D IC Test Through Power Line Methodology Alberto Pagani, Alessandro Motta � STMicroelectronics, IT
9:15 - 9:40	In-Place Signal and Power Noise Waveform Capturing Within 3D Chip Stacking Makoto Nagata, Satoshi Takaya � Kobe Univ., JP; Hiroaki Ikeda � ASET, JP
9:40 - 10:05	Testing Leakage Faults of Power TSV in 3D IC Chi-Hih Shih, Shih-An Hsieh, Yi-Chang Lu, James C.-M. Li, Tzong-Lin Wu � National Taiwan Univ., TW; Krishnendu Chakrabarty � Duke University, USA

10:05 AM - 10:30 AM	Session 6 - Table-Top Demos (Coffee & Tea Provided)
	Demo 1: An Innovative Method for 2.5D/3D IC Interconnection Integrity Monitoring Hans Manhaeve – Ridgetop Europe, BE; Andrew Levy – Ridgetop, USA; Chih-Yang Li – ALLVia, USA Demo 2: Pyramid Probe Card Ken Smith – Cascade Microtech, USA Demo 3: IEEE 1149.1-2013 Support for 3D Stacked Die Brian Turmelle, Mike Ecker, Craig Stephan, CJ Clark – Intellitech, USA Demo 4: Synopsys Synthesis-Based 3D-IC Test Avetik Yessayan, Yervant Zorian, Adam Cron – Synopsys, USA

10:30 AM - 11:20 AM	Session 7 - 3D Wafer Probing Chair: First Last (Affiliation)
10:30 - 10:55	Signal Integrity Design for Wide IO and 3D-TSV IC Test at Wafer Probe Ken Smith, Daniel Bock � Cascade Microtech, USA
10:55 - 11:20	Very Low Damage Direct Testing of Micro-Bumps for 3D IC Integration Onnik Yaglioglu, Ben Eldridge � FormFactor, USA; Shoji Wada, Toru Ishikawa � Elpida Memory, JP

11:20 AM - 12:30 PM	Session 8 - Panel Discussion: How Will 3D-Testing Change the Test Supply Chain?
	Panelists: Adam Cron – Principal Engineer DfT – Synopsys, USA Gary Fleeman – VP of Marketing – Advantest, USA TM Mak – Director 2.5D/3D DfT Strategy – GlobalFoundries, USA Erik Jan Marinissen – Principal Scientist – IMEC, BE Daniel Rishavy – TEL Test Systems, USA tbd – Amkor, USA 3D IC stacking is more intricate than 2D assembly and requires elaborate testers to perform fully functional test. Built-in self-test adds cost and takes die real estate. Going to 3D means re-thinking the test strategy from what it was in the past, especially in terms of economics. Panelists from across the test value chain will discuss strategies to address the unique circumstances surrounding 3D IC testing.

12:20 PM - 1:20 PM WORKSHOP LUNCHEON

1:20 PM - 3:00 PM	Session 9 - 3D Design-for-Test
1:20 - 1:45	3D Design-for-Test Architectures Based on IEEE P1687 Yassine Fkih, Pascal Vivet � CEA-Leti, FR; Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale � LIRMM, FR; J�rgen Schl�ffel � Mentor Graphics, DE
1:45 - 2:10	Development of Testing Technology for Wide Bus Chip-to-Chip Interconnection in 3D LSI Chip Stacking System Masahiro Aoyagi, Fumito Imura, Samson Melamed, Shunsuke Nemoto, Naoya Watanabe, Katsuya Kikuchi, Hiroshi Nakagawa � AIST, JP; Michiya Hagimoto, Yuko Matsumoto � TOPS Systems Corporation, JP
2:10 - 2:35	Expandable and Reliable 2.5D SOC Design with Reconfigurable Logic Dies Li Jiang, Feng Yuan, Qiang Xu – Chinese Univ. of Hong Kong, HK; William Eklow – Cisco Systems, USA
2:35 - 3:00	TSVs Pre-Bond Testing: A Test Scheme for Capturing BIST Responses Under PVT Variations Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Hakim Zimouche � LIRMM, FR

3:00 PM - 4:00 PM	Session 10 - Special Session on 2013 3DInCites Awards Nominees in the Category Test & Reliability Tools and Equipment
	Moderator: Françoise von Trapp – Queen of 3D, Founder/Director 3DInCites, USA Nominees: Encounter Test: Brion Keller – Cadence Design Systems, USA Tessent MemoryBIST: Tbd – Mentor Graphics, USA CM300 Probe Station: Ken Smith – Cascade Microtech, USA NanoPierce Contactor: Mike Slessor – FormFactor, USA InStrip3D: Tbd – Multitest, USA NSX320 Metrology Series: David Grant – Rudolph Technologies, USA This special session features the nominees and the winner of the 2013 3DInCites Awards' Test and Reliability Tools and Equipment category. Moderated by Françoise von Trapp (Queen of 3D), each panelist will briefly introduce the product that was nominated for the award, and discuss the technical merits. The remainder of the session will be in a Q&A discussion format, focused on these innovative solutions for 3D IC test and reliability including design for test solutions, probe card and test contactor technology, built-in-self test for memory, test handlers, and inspection and metrology for TSV reliability.

4:00 PM WORKSHOP CLOSURE

More Information

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Yervant Zorian – General Chair
Synopsys
700 East Middlefield Road
Mountain View, CA 94043-4033, USA
Tel.: +1 (650) 584-7120
E-mail: yervant.zorian@synopsys.com

Erik Jan Marinissen – Program Chair
IMEC
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 16 28-8755
E-mail: erik.jan.marinissen@imec.be

Committees

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General Chair:
Y. Zorian – Synopsys (US)

Program Chairs:
E.J. Marinissen – IMEC (BE)

Finance Chair:
B. Eklow – Cisco Systems (US)

Publication Chair:
L. Ciganda – Politecnico di Torino (IT)

Publicity Chair:
F. von Trapp – 3DInCites (US)

Web Chair:
G. Jervan – Tallinn Univ. of Techn. (EE)

Arrangements Chair:
J. Potter – Asset Intertech (US)

Program Committee Members:
S. Adham – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
S. Bhatia – Oasys (US)
K. Chakrabarty – Duke Univ. (US)
S. Chakravarty – LSI (US)
V. Chickermane – Cadence (US)
K.Y. Chung – Samsung (KR)
E. Cormack – DfT Solutions (UK)
A. Cron – Synopsys (US)
A. Crouch – Asset Intertech (US)
G. Fleeman – Advantest (US)
M.-L. Flottes – LIRMM (FR)
P. Franzon – NC State Univ. (US)
S.K. Goel – TSMC (US)
S. Hamdioui – TU Delft (NL)
G. Harutyunyan – Synopsys (AM)
M. Higgins – Analog Devices (IRL)
C.-L. Hsu – ITRI (TW)
S.-Y. Huang – NTHU (TW)
M. Hutner – Teradyne (US)
S. Kameyama – Fujitsu (JP)
M. Knox – IBM (US)
M. Laisne – Qualcomm (US)
S. Lecomte – ST-Ericsson (FR)
K.H. Lee – GigaLane (KR)
A. Leong – FormFactor (US)
I. Loi – Universita di Bologna (IT)
M. Loranger – FormFactor (US)
R.Z. Makki – GlobalFoundries (US)
C. Mayor – Presto Engineering (FR)
T. McLaurin – ARM (US)
B. Nadeau-Dostie – Mentor Graph. (US)
B. Patti – Tezzaron Semiconductor (US)
F. Pöhl – Intel (DE)
M. Ricchetti – AMD (US)
D. Rishavy – TEL Test Systems (US)
S. Shaikh – Broadcom (US)
T. Thärigen – Cascade Microtech (DE)
P. Vivet – CEA-Leti (FR)
Q. Xu – Chinese Univ. Hong Kong (HK)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST 2013) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).